--

-- ****************************************************************************
--                                                                           --
--     Copyright @ 1999                                                      --
--                                                                           --
--     Tetraedre SARL,  chenes 19,   2072 Saint-Blaise,  Switzerland         --
--                                                                           --
-- ****************************************************************************
--                                                                           --
-- Filename  : tctf1_bench.vhd                                               --
--                                                                           --
-- ****************************************************************************
--                                                                           --
-- WARNING: This file is the property of Tetraedre SARL, Switzerland. This   --
-- file is protected by a copyright. The reading, copying, compilation,      --
-- synthesis and other use of this file is forbidden without a written       --
-- agreement signed by Tetraedre SARL, Switzerland.                          --
--                                                                           --
-- IN NO EVENT SHALL TETRAEDRE SARL BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER--
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING   --
-- FROM, OUT OF OR IN CONNECTION WITH THIS DESCRIPTION OR THE USE OF IT.     --
--                                                                           --
-- ****************************************************************************








---------- Entity bench_tctf1 ---------- 
library ieee;
use ieee.std_logic_1164.all;
entity tctf1_bench is
end;


---------- Architecture bench_tctf1 ---------- 
library ieee, work;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

architecture simple of tctf1_bench is
    signal iv      : std_logic_vector(63 downto 0);
    signal key1    : std_logic_vector(63 downto 0);
    signal key2    : std_logic_vector(63 downto 0);
    signal key3    : std_logic_vector(63 downto 0);
    signal first   : std_logic;
    signal do_next : std_logic;
    signal crypt   : std_logic;
    signal clk     : std_logic;
    signal d       : std_logic;
    signal q       : std_logic;
    signal done    : std_logic;
    signal erreur  : std_logic;
    signal nreset  : std_logic;

    component tctf1 
    port (
         iv      : in  std_logic_vector(63 downto 0);
         key1    : in  std_logic_vector(63 downto 0);
         key2    : in  std_logic_vector(63 downto 0);
         key3    : in  std_logic_vector(63 downto 0);
         first   : in  std_logic;
         do_next : in  std_logic;
         crypt   : in  std_logic;
         clk     : in  std_logic;
         nreset  : in  std_logic;
         d       : in  std_logic;
         q       : out std_logic;
         done    : out std_logic
    );
    end component;


begin
    i_tctf1 : tctf1
    port map (
        iv      => iv,
        key1    => key1,
        key2    => key2,
        key3    => key3,
        first   => first,
        do_next => do_next,
        crypt   => crypt,
        clk     => clk,
        nreset  => nreset,
        d       => d,
        q       => q,
        done    => done
    );


    process
    begin
        nreset <= '0';
        wait for 100 ns;
        nreset <= '1';
        wait;
    end process;



    P43 : process
    begin
        clk <= '0';
        wait for 500 ns;
        clk <= '1';
        wait for 500 ns;
    end process;


    -- ********************************************************
    -- ****                TEST PROCEDURE                  ****
    -- ********************************************************
    P44 : process
    procedure tctf_test(constant xdatain  : in  std_logic;
                        constant xexpect  : in  std_logic;
                        constant xfirst   : in  std_logic;
                        constant xcrypt   : in  std_logic) is
    begin
        crypt   <= xcrypt;
        first   <= xfirst;
        d       <= xdatain;
        do_next <= '1';
        wait for 1000 ns;
        do_next <= '0';
        d       <= '0';
        wait on done;
        wait for 400 ns;
        assert q=xexpect report "------- !!! ERROR !!! " severity error;
        if (q/=xexpect) then
            erreur <= '1';
        end if;
        wait for 50 ns;
    end tctf_test;


    -- ********************************************************
    -- ****                TEST VECTORS                    ****
    -- ********************************************************

    begin
        erreur  <= '0';
        do_next <= '0';
        first   <= '0';
        wait for 2000 ns;
        
        key1 <= to_stdlogicvector(X"0123456789ABCDEF");
        key2 <= to_stdlogicvector(X"23456789ABCDEF01");
        key3 <= to_stdlogicvector(X"456789ABCDEF0123");
        iv   <= to_stdlogicvector(X"1234567890ABCDEF");
        
        tctf_test('0','1','1','1');
        wait for 5 us;
        tctf_test('1','1','0','1');
        tctf_test('1','0','0','1');


        ASSERT false REPORT "*****WARNING: TEST NOT COMPLETE !!!!!!!!!!******"
        SEVERITY note;
        wait;


        ASSERT erreur='0' REPORT "FINAL REPORT : TEST BENCH FAILED !!"
        SEVERITY error;

        ASSERT erreur='1' REPORT "FINAL REPORT : TEST BENCH SUCCESSFULL !"
        SEVERITY note;
        wait;

    end process;

end simple;