-- -- **************************************************************************** -- -- -- Copyright @ 1999 -- -- -- -- Tetraedre SARL, chenes 19, 2072 Saint-Blaise, Switzerland -- -- -- -- **************************************************************************** -- -- -- Filename : tctf8_bench.vhd -- -- -- -- **************************************************************************** -- -- -- WARNING: This file is the property of Tetraedre SARL, Switzerland. This -- -- file is protected by a copyright. The reading, copying, compilation, -- -- synthesis and other use of this file is forbidden without a written -- -- agreement signed by Tetraedre SARL, Switzerland. -- -- -- -- IN NO EVENT SHALL TETRAEDRE SARL BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER-- -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -- -- FROM, OUT OF OR IN CONNECTION WITH THIS DESCRIPTION OR THE USE OF IT. -- -- -- -- **************************************************************************** ---------- Entity bench_tctf8 ---------- library ieee; use ieee.std_logic_1164.all; entity tctf8_bench is end; ---------- Architecture bench_tctf8 ---------- library ieee, work; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; architecture simple of tctf8_bench is signal iv : std_logic_vector(63 downto 0); signal key1 : std_logic_vector(63 downto 0); signal key2 : std_logic_vector(63 downto 0); signal key3 : std_logic_vector(63 downto 0); signal first : std_logic; signal do_next : std_logic; signal crypt : std_logic; signal clk : std_logic; signal d : std_logic_vector(7 downto 0); signal q : std_logic_vector(7 downto 0); signal done : std_logic; signal erreur : std_logic; signal nreset : std_logic; component tctf8 port ( iv : in std_logic_vector(63 downto 0); key1 : in std_logic_vector(63 downto 0); key2 : in std_logic_vector(63 downto 0); key3 : in std_logic_vector(63 downto 0); first : in std_logic; do_next : in std_logic; crypt : in std_logic; clk : in std_logic; nreset : in std_logic; d : in std_logic_vector( 7 downto 0); q : out std_logic_vector( 7 downto 0); done : out std_logic ); end component; begin i_tctf8 : tctf8 port map ( iv => iv, key1 => key1, key2 => key2, key3 => key3, first => first, do_next => do_next, crypt => crypt, clk => clk, nreset => nreset, d => d, q => q, done => done ); process begin nreset <= '0'; wait for 100 ns; nreset <= '1'; wait; end process; P43 : process begin clk <= '0'; wait for 500 ns; clk <= '1'; wait for 500 ns; end process; -- ******************************************************** -- **** TEST PROCEDURE **** -- ******************************************************** P44 : process procedure tctf_test(constant xdatain : in bit_vector(7 downto 0); constant xexpect : in bit_vector(7 downto 0); constant xfirst : in std_logic; constant xcrypt : in std_logic) is variable expect : std_logic_vector(7 downto 0); begin crypt <= xcrypt; first <= xfirst; d <= to_stdlogicvector(xdatain); do_next <= '1'; wait for 1000 ns; do_next <= '0'; d <= (others=>'0'); wait on done; wait for 400 ns; expect := to_stdlogicvector(xexpect); assert q=expect report "------- !!! ERROR !!! " severity error; if (q/=expect) then erreur <= '1'; end if; wait for 50 ns; end tctf_test; -- ******************************************************** -- **** TEST VECTORS **** -- ******************************************************** begin erreur <= '0'; do_next <= '0'; first <= '0'; wait for 2000 ns; key1 <= to_stdlogicvector(X"0123456789ABCDEF"); key2 <= to_stdlogicvector(X"23456789ABCDEF01"); key3 <= to_stdlogicvector(X"456789ABCDEF0123"); iv <= to_stdlogicvector(X"1234567890ABCDEF"); tctf_test(X"4E",X"EE",'1','1'); wait for 5 us; tctf_test(X"6F",X"9B",'0','1'); tctf_test(X"77",X"04",'0','1'); tctf_test(X"20",X"FF",'0','1'); tctf_test(X"69",X"CA",'0','1'); tctf_test(X"73",X"CE",'0','1'); tctf_test(X"20",X"C8",'0','1'); tctf_test(X"74",X"06",'0','1'); tctf_test(X"68",X"70",'0','1'); tctf_test(X"65",X"60",'0','1'); tctf_test(X"EE",X"4E",'1','0'); tctf_test(X"9B",X"6F",'0','0'); tctf_test(X"04",X"77",'0','0'); tctf_test(X"FF",X"20",'0','0'); tctf_test(X"CA",X"69",'0','0'); tctf_test(X"CE",X"73",'0','0'); tctf_test(X"C8",X"20",'0','0'); tctf_test(X"06",X"74",'0','0'); tctf_test(X"70",X"68",'0','0'); tctf_test(X"60",X"65",'0','0'); -- ****************************************************** key1 <= to_stdlogicvector(X"B63ADFD042D8A232"); key2 <= to_stdlogicvector(X"71549DAE7248ECAF"); key3 <= to_stdlogicvector(X"44A19D427A54CAED"); iv <= to_stdlogicvector(X"9F76DC32BF32BD06"); tctf_test(X"45",X"24",'1','1'); tctf_test(X"F4",X"95",'1','1'); tctf_test(X"83",X"A7",'0','1'); tctf_test(X"C0",X"9E",'0','1'); tctf_test(X"01",X"F6",'0','1'); tctf_test(X"89",X"AE",'0','1'); tctf_test(X"45",X"C0",'0','1'); tctf_test(X"F4",X"63",'0','1'); tctf_test(X"83",X"F3",'0','1'); tctf_test(X"7D",X"F0",'0','1'); tctf_test(X"F4",X"EE",'0','1'); tctf_test(X"08",X"A2",'0','1'); tctf_test(X"7D",X"D2",'0','1'); tctf_test(X"69",X"21",'0','1'); tctf_test(X"C7",X"71",'0','1'); tctf_test(X"45",X"CE",'0','1'); tctf_test(X"F8",X"B6",'0','1'); tctf_test(X"00",X"70",'0','1'); tctf_test(X"00",X"17",'0','1'); tctf_test(X"00",X"B1",'0','1'); tctf_test(X"00",X"7B",'0','1'); tctf_test(X"C7",X"CE",'0','1'); tctf_test(X"45",X"27",'0','1'); tctf_test(X"F0",X"C1",'0','1'); tctf_test(X"00",X"4D",'0','1'); tctf_test(X"00",X"47",'0','1'); tctf_test(X"00",X"09",'0','1'); tctf_test(X"00",X"E5",'0','1'); tctf_test(X"EB",X"70",'0','1'); tctf_test(X"09",X"17",'0','1'); tctf_test(X"8B",X"BA",'0','1'); tctf_test(X"4D",X"07",'0','1'); -- ****************************************************** key1 <= to_stdlogicvector(X"232A8D240DFDA36B"); key2 <= to_stdlogicvector(X"FACE8427EAD94517"); key3 <= to_stdlogicvector(X"4D4EAA1C94D54A27"); iv <= to_stdlogicvector(X"92FB7562D3C00396"); tctf_test(X"F0",X"39",'1','1'); tctf_test(X"83",X"4A",'1','1'); tctf_test(X"C1",X"55",'0','1'); tctf_test(X"01",X"79",'0','1'); tctf_test(X"89",X"A7",'0','1'); tctf_test(X"4D",X"5F",'0','1'); tctf_test(X"F0",X"54",'0','1'); tctf_test(X"83",X"D5",'0','1'); tctf_test(X"7D",X"33",'0','1'); tctf_test(X"F0",X"8D",'0','1'); tctf_test(X"08",X"EB",'0','1'); tctf_test(X"7D",X"27",'0','1'); tctf_test(X"31",X"ED",'0','1'); tctf_test(X"8B",X"7F",'0','1'); tctf_test(X"55",X"41",'0','1'); tctf_test(X"F8",X"BC",'0','1'); tctf_test(X"D1",X"7F",'0','1'); tctf_test(X"E2",X"14",'0','1'); tctf_test(X"89",X"02",'0','1'); tctf_test(X"55",X"AE",'0','1'); tctf_test(X"F8",X"2F",'0','1'); tctf_test(X"8B",X"99",'0','1'); tctf_test(X"45",X"98",'0','1'); tctf_test(X"F4",X"8A",'0','1'); tctf_test(X"8B",X"25",'0','1'); tctf_test(X"4D",X"F2",'0','1'); tctf_test(X"F0",X"5A",'0','1'); tctf_test(X"8D",X"D9",'0','1'); tctf_test(X"54",X"CE",'0','1'); tctf_test(X"C1",X"D7",'0','1'); tctf_test(X"01",X"E7",'0','1'); tctf_test(X"52",X"A9",'0','1'); -- ////////////////////////////// DECODE //////////////////// key1 <= to_stdlogicvector(X"B63ADFD042D8A232"); key2 <= to_stdlogicvector(X"71549DAE7248ECAF"); key3 <= to_stdlogicvector(X"44A19D427A54CAED"); iv <= to_stdlogicvector(X"9F76DC32BF32BD06"); tctf_test(X"24",X"45",'1','0'); tctf_test(X"95",X"F4",'1','0'); tctf_test(X"A7",X"83",'0','0'); tctf_test(X"9E",X"C0",'0','0'); tctf_test(X"F6",X"01",'0','0'); tctf_test(X"AE",X"89",'0','0'); tctf_test(X"C0",X"45",'0','0'); tctf_test(X"63",X"F4",'0','0'); tctf_test(X"F3",X"83",'0','0'); tctf_test(X"F0",X"7D",'0','0'); tctf_test(X"EE",X"F4",'0','0'); tctf_test(X"A2",X"08",'0','0'); tctf_test(X"D2",X"7D",'0','0'); tctf_test(X"21",X"69",'0','0'); tctf_test(X"71",X"C7",'0','0'); tctf_test(X"CE",X"45",'0','0'); tctf_test(X"B6",X"F8",'0','0'); tctf_test(X"70",X"00",'0','0'); tctf_test(X"17",X"00",'0','0'); tctf_test(X"B1",X"00",'0','0'); tctf_test(X"7B",X"00",'0','0'); tctf_test(X"CE",X"C7",'0','0'); tctf_test(X"27",X"45",'0','0'); tctf_test(X"C1",X"F0",'0','0'); tctf_test(X"4D",X"00",'0','0'); tctf_test(X"47",X"00",'0','0'); tctf_test(X"09",X"00",'0','0'); tctf_test(X"E5",X"00",'0','0'); tctf_test(X"70",X"EB",'0','0'); tctf_test(X"17",X"09",'0','0'); tctf_test(X"BA",X"8B",'0','0'); tctf_test(X"07",X"4D",'0','0'); -- ****************************************************** key1 <= to_stdlogicvector(X"232A8D240DFDA36B"); key2 <= to_stdlogicvector(X"FACE8427EAD94517"); key3 <= to_stdlogicvector(X"4D4EAA1C94D54A27"); iv <= to_stdlogicvector(X"92FB7562D3C00396"); tctf_test(X"39",X"F0",'1','0'); tctf_test(X"4A",X"83",'1','0'); tctf_test(X"55",X"C1",'0','0'); tctf_test(X"79",X"01",'0','0'); tctf_test(X"A7",X"89",'0','0'); tctf_test(X"5F",X"4D",'0','0'); tctf_test(X"54",X"F0",'0','0'); tctf_test(X"D5",X"83",'0','0'); tctf_test(X"33",X"7D",'0','0'); tctf_test(X"8D",X"F0",'0','0'); tctf_test(X"EB",X"08",'0','0'); tctf_test(X"27",X"7D",'0','0'); tctf_test(X"ED",X"31",'0','0'); tctf_test(X"7F",X"8B",'0','0'); tctf_test(X"41",X"55",'0','0'); tctf_test(X"BC",X"F8",'0','0'); tctf_test(X"7F",X"D1",'0','0'); tctf_test(X"14",X"E2",'0','0'); tctf_test(X"02",X"89",'0','0'); tctf_test(X"AE",X"55",'0','0'); tctf_test(X"2F",X"F8",'0','0'); tctf_test(X"99",X"8B",'0','0'); tctf_test(X"98",X"45",'0','0'); tctf_test(X"8A",X"F4",'0','0'); tctf_test(X"25",X"8B",'0','0'); tctf_test(X"F2",X"4D",'0','0'); tctf_test(X"5A",X"F0",'0','0'); tctf_test(X"D9",X"8D",'0','0'); tctf_test(X"CE",X"54",'0','0'); tctf_test(X"D7",X"C1",'0','0'); tctf_test(X"E7",X"01",'0','0'); tctf_test(X"A9",X"52",'0','0'); ASSERT erreur='0' REPORT "FINAL REPORT : TEST BENCH FAILED !!" SEVERITY error; ASSERT erreur='1' REPORT "FINAL REPORT : TEST BENCH SUCCESSFULL !" SEVERITY note; wait; end process; end simple;