-- ####################################################################
library ieee;
use ieee.std_logic_1164.all;

entity timer2l_bench is
end;

   -- ##################################################################

library ieee, work;
use ieee.std_logic_1164.all;
use std.textio.all;

architecture simple of timer2l_bench is


    component timer2l
    port (
         clk       : in    std_logic;
         nreset    : in    std_logic;
         nrdcs     : in    std_logic;
         nwrcs     : in    std_logic;
         addr      : in    std_logic_vector( 3 downto 0);
         dwrite    : in    std_logic_vector( 7 downto 0);
         dread     : out   std_logic_vector( 7 downto 0);
        
         -- .................... applic's specific I/O
         nirq      : out   std_logic
         );
    end component ;

    signal clk       : std_logic;
    signal nreset    : std_logic;
    signal nrdcs     : std_logic;
    signal nwrcs     : std_logic;
    signal addr      : std_logic_vector( 3 downto 0);
    signal dwrite    : std_logic_vector( 7 downto 0);
    signal dread     : std_logic_vector( 7 downto 0);
    signal nirq      : std_logic;

begin

    i_dev : timer2l
    port map (
         clk        => clk        ,
         nreset     => nreset     ,
         nrdcs      => nrdcs      ,
         nwrcs      => nwrcs      ,
         addr       => addr       ,
         dread      => dread      ,
         dwrite     => dwrite     ,
         nirq       => nirq       
    );

    
    process
    begin
        clk <= '0';
        wait for 50 ns;
        clk <= '1';
        wait for 50 ns;
    end process;


    process
    begin
        nreset <= '0';
        wait for 179 ns;
        nreset <= '1';
        wait;
    end process;


    -- //////////////////////////////////////////////////////////////////
    -- /////////////////// TEST PROCEDURES //////////////////////////////
    -- /////////////////////////////////////////////////////////////////

    process
        procedure echo (constant texte : in string) is
            variable s : line;
        begin
            write(s,texte);
            writeline(output,s);
        end echo;

        procedure wr (constant adata : in std_logic_vector(7 downto 0);
                      constant aaddr : in std_logic_vector(7 downto 0)) is
        begin
            addr   <= addr(3 downto 0);
            dwrite <= adata;
            nwrcs  <= '1';
            wait for 10 ns;
            nwrcs  <= '0';
            wait for 80 ns;
            nwrcs  <= '1';
            wait for 10 ns;
        end wr;

        procedure rd (constant adata : in std_logic_vector(7 downto 0);
                      constant aaddr : in std_logic_vector(7 downto 0)) is
        begin
            addr   <= addr(3 downto 0);
            dwrite <= adata;
            nrdcs  <= '1';
            wait for 10 ns;
            nrdcs  <= '0';
            wait for 80 ns;
            assert dread=adata report "ERROR: rd() failed" severity error;
            nrdcs  <= '1';
            wait for 10 ns;
        end rd;

        procedure cycle (constant nbr : in integer) is
        begin
            for i in 0 to nbr-1 loop
                wait for 100 ns;
            end loop;
        end cycle;

    -- ============================================================
    begin
        echo("---------------- TEST START ---");
        cycle(5);
        wr(X"14",X"10");     -- Prescaler 20
        cycle(5);
        wr(X"05",X"11");
        wr(X"06",X"12");
        wr(X"03",X"14");
        rd(X"07",X"EA");
    
        wait for 400 us;
        wr(X"16",X"12");
 
        assert nirq='0' report "ERROR: expected interrupt now !" severity 
error;
        wr(X"01",X"14");
        rd(X"07",X"E2");

        echo("---------------- DONE --------");
        wait;
    end process;
    

end simple;