-- ---------------------------------------------------------------- --
-- Compteur 4 bits avec reset asynchrone                            --
-- Thierry Schneider, 25 juillet 2000                               --
-- ---------------------------------------------------------------- --

library ieee;
use ieee.std_logic_1164.all;

entity cnt4 is
port (
        nreset   : in  std_logic;
        cnt      : out std_logic_vector(3 downto 0);
        clk      : in  std_logic 
     );
end;



library ieee; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_unsigned.all

architecture simple of cnt4 is

    signal int_cnt      : std_logic_vector(3 downto 0);
    signal next_cnt     : std_logic_vector(3 downto 0);
    
begin

    next_cnt <= int_cnt + "1";
    
    process(clk, nreset)
    begin
        if (nreset='0') then
            int_cnt <= (others => '0');
        else
            if (clk='1' and clk'event) then
                int_cnt <= next_cnt;
            end if;
        end if;
    end process;

    cnt <= int_cnt;
    
end simple;