-- ---------------------------------------------------------------- --
-- Canvas pour les composants VHDL                                  --
-- Thierry Schneider, 7 août 2000                                   --
-- ---------------------------------------------------------------- --

library ieee;
use ieee.std_logic_1164.all;

entity cnt4 is
port (
        a        : in  std_logic;
        b        : in  std_logic;
        clock    : in  std_logic;
        nreset   : in  std_logic;
        q        : out std_logic_vector(3 downto 0);
        s        : out std_logic 
     );
end;



library ieee; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_unsigned.all

architecture simple of cnt4 is

    signal int_q      : std_logic_vector(3 downto 0);
    signal next_q     : std_logic_vector(3 downto 0);
    signal int_v      : std_logic_vector(7 downto 0);
    signal next_v     : std_logic_vector(7 downto 0);
    
begin

--------------------------------------- COMBINATORIAL ---------------
    next_v <= ...
    
    int_s  <= ...

    process(int_q, int_v, a,)
        variable tmp_q : std_logic_vector(3 downto 0);
    begin
        tmp_q := ...

        ...

        next_q <= tmp_q
    end process

--------------------------------------- REGISTERS ---------------
    process(clk, nreset)
    begin
        if (nreset='0') then
            int_q <= (others => '0');
            int_v <= (others => '0');
        else
            if (clk='1' and clk'event) then
                int_q <= next_q;
                int_v <= next_v;
            end if;
        end if;
    end process;

--------------------------------------- OUTPUTS ---------------
    q <= int_q; 
    s <= int_s;

end process;