library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity alu_slice is
    port (
        g      : in   std_logic_vector(3 downto 0);
        p      : in   std_logic_vector(3 downto 0);
        a      : in   std_logic;
        b      : in   std_logic;
        ci     : in   std_logic;
        s      : out  std_logic;
        co     : out  std_logic
        );
end;


library ieee;
use ieee.std_logic_1164.all;

architecture simple of alu_slice is
    signal gi01     : std_logic;
    signal gi23     : std_logic;
    signal gi       : std_logic;
    signal pi       : std_logic;
    signal pi01     : std_logic;
    signal pi23     : std_logic;
begin
    
    gi01 <= g(0)   when (b='0') else g(1);
    gi23 <= g(2)   when (b='0') else g(3);

    pi01 <= p(0)   when (b='0') else p(1);
    pi23 <= p(2)   when (b='0') else p(3);
    
    gi   <= gi01   when (a='0') else gi23;
    pi   <= pi01   when (a='0') else pi23;

    s    <= gi xor ci;
    co   <= pi or (gi and ci);
end simple;