library ieee, work;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity divsyn is
    port (
        a            : in  std_logic_vector(3 downto 0);
        b            : in  std_logic_vector(1 downto 0);
        s            : out std_logic_vector(3 downto 0);
        
        clock_input  : in  std_logic;
        nreset       : in  std_logic
        );
end entity;

architecture simple of divsyn is
    signal next_cnt2: std_logic_vector(2 downto 0);
    signal next_cnt : std_logic_vector(2 downto 0);
    signal cnt      : std_logic_vector(2 downto 0);
    signal next_clk : std_logic;
    signal clk      : std_logic;
    
    signal int_s    : std_logic_vector(3 downto 0);
    signal next_s   : std_logic_vector(3 downto 0);
begin

-- //////////////////////////////////////////////////////////////////////
-- /////////////////////////// Synchronous divider by 5 /////////////////
-- //////////////////////////////////////////////////////////////////////
    next_cnt <= "000"      when (cnt="100") else
                cnt + "1";
    next_cnt2<= "000"      when (next_cnt="XXX") else next_cnt;
    -- X states filtering for start-up of the counter without reset
    
    next_clk <= '1'        when (cnt="100") else 
                '0'        when (cnt="010") else
                clk;
                
    process(clock_input)
    begin
        if (clock_input='1' and clock_input'event) then
            clk <= next_clk;
            cnt <= next_cnt2;
        end if;
    end process;
    
-- //////////////////////////////////////////////////////////////////////
-- /////////////////////////// Synchronous state machine ////////////////
-- //////////////////////////////////////////////////////////////////////
   
   next_s <= a          when (b="00") else
             int_s + a  when (b="01") else
             int_s - a  when (b="10") else
             int_s;
        

    process(clk, nreset)
    begin
        if (nreset='0') then
            int_s <= (others => '0');
        else
            if (clk='1' and clk'event) then
                int_s <= next_s;
            end if;
        end if;
    end process;

    s <= int_s;
    
end simple;