-- ////////////////////////////////////////////////////////////////////////
-- //////////////////////////  ENTITY /////////////////////////////////////
-- ////////////////////////////////////////////////////////////////////////

library ieee;
use ieee.std_logic_1164.all;


entity  basic_function is
    port (
        a              : in  std_logic;
        b              : in  std_logic;
        c              : in  std_logic;

        s              : out std_logic;

        clk            : in  std_logic;
        nreset         : in  std_logic;
        
        shiftmode      : in  std_logic;
        sdi            : in  std_logic;
        sdo            : out std_logic
        );
end basic_function;
 
 

-- ////////////////////////////////////////////////////////////////////////
-- /////////////////////////////  ARCHITECTURE ////////////////////////////
-- ////////////////////////////////////////////////////////////////////////

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;


architecture simple of basic_function is

    signal int_a    : std_logic;
    signal int_b    : std_logic;
    signal int_c    : std_logic;
    signal int_s    : std_logic;
    
    signal next_a   : std_logic;
    signal next_b   : std_logic;
    signal next_c   : std_logic;
    signal next_s   : std_logic;
    
    signal calc_s   : std_logic;
begin

    -- ......................................................
    -- ............... Assignation des entrees/sorties ......
    -- ......................................................

    next_a <= a when (shiftmode='0') else sdi;
    next_b <= b when (shiftmode='0') else int_a;
    next_c <= c when (shiftmode='0') else int_b;

    s      <= int_s;
    sdo    <= int_s;

    -- ......................................................
    -- ........................ Combinatoire ................
    -- ......................................................

    calc_s <= int_c and (int_b xor (int_a and int_b));
        
        
    next_s <= calc_s when (shiftmode='0') else int_c;
    
    -- ......................................................
    -- ........................ Registres ...................
    -- ......................................................

    process(clk, nreset)
    begin
        if (nreset='0') then
            int_a <= '0';
            int_b <= '0';
            int_c <= '0';
            int_s <= '0';
        else
            if (clk='1' and clk'event) then
                int_a <= next_a;
                int_b <= next_b;
                int_c <= next_c;
                int_s <= next_s;
            end if;
        end if;
    end process;

    -- ......................................................

end simple;
-- ////////////////////////////////////////////////////////////////////////