-- ////////////////////////////////////////////////////////////////////////
-- //////////////////////////  ENTITY /////////////////////////////////////
-- ////////////////////////////////////////////////////////////////////////

library ieee;
use ieee.std_logic_1164.all;


entity  basic_function is
    port (
        a              : in  std_logic;
        b              : in  std_logic;
        c              : in  std_logic;

        s              : out std_logic;

        system         : in  std_logic_vector(2 downto 0);
        sdi            : in  std_logic;
        sdo            : out std_logic
        );
end basic_function;
 
 

-- ////////////////////////////////////////////////////////////////////////
-- //////////////////////////  ARCHITECTURE ///////////////////////////////
-- ////////////////////////////////////////////////////////////////////////

library ieee, work;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.memories_pack.all;

architecture simple of basic_function is
 
    signal int_a         : std_logic;
    signal int_b         : std_logic;
    signal int_c         : std_logic;
    
    signal in_reg        : std_logic_vector(2 downto 0);
    signal next_in_reg   : std_logic_vector(2 downto 0);

    signal calc_s        : std_logic;
    signal tmp_sd0       : std_logic;
    
begin

    -- ......................................................
    -- ............... Assignation des entrees/sorties ......
    -- ......................................................

    next_in_reg <= a & b & c;   
  
    int_a <= in_reg(2);   -- !!!! ATTENTION, respecter l'ordre
    int_b <= in_reg(1);   -- d'assignation
    int_c <= in_reg(0);

    -- ......................................................
    -- ........................ Combinatoire ................
    -- ......................................................

    calc_s <= int_c and (int_b xor (int_a and int_b));
    
    -- ......................................................
    -- ........................ Registres ...................
    -- ......................................................
i_input_reg : memr3 port map (next_in_reg, in_reg, system, sdi  , tmp_sd0);
i_out_reg   : memr1 port map (calc_s,      s     , system, tmp_sd0, sdo  );
    -- ......................................................

end simple;
-- ////////////////////////////////////////////////////////////////////////