-- ////////////////////////////////////////////////////////////////////////
-- //////////////////////////  ENTITY /////////////////////////////////////
-- ////////////////////////////////////////////////////////////////////////

library ieee;
use ieee.std_logic_1164.all;


entity  memr3 is
    port (
        d              : in  std_logic_vector(2 downto 0);
        q              : in  std_logic_vector(2 downto 0);
        system         : in  std_logic_vector(2 downto 0);
        sdi            : in  std_logic;
        sdo            : out std_logic
        );
end memr4;
 
 

-- ////////////////////////////////////////////////////////////////////////
-- //////////////////////////  ARCHITECTURE ///////////////////////////////
-- ////////////////////////////////////////////////////////////////////////

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;


architecture simple of memr3 is

    signal int_q    : std_logic_vector(2 downto 0);
    signal next_q   : std_logic_vector(2 downto 0);

begin


    next_q <= d when (system(SYS_TEST)='0') else int_q(1 downto 0) & sdi;
    sdo    <= int_q(2);
    
    
    -- ......................................................
    -- ........................ Registres ...................
    -- ......................................................

    process(system)
    begin
        if (system(SYS_RST)='0') then
            int_q <= (others => '0');
        else
            if (system(SYS_CLOCK)='1' and system(SYS_CLOCK)'event) then
                int_q <= next_q;
            end if;
        end if;
    end process;

    -- ......................................................

end simple;
-- ////////////////////////////////////////////////////////////////////////