-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library ieee;
use ieee.std_logic_1164.all;

entity gated_clock is
    port (
        en      : in  std_logic;
        clk_in  : in  std_logic;
        clk_out : out std_logic
    );
end gated_clock;

library ieee;
use ieee.std_logic_1164.all;

architecture struct of gated_clock is 
begin
    clk_out <= clk_in and en;
end struct;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
   
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library ieee;
use ieee.std_logic_1164.all;

entity reg_ctrl is
    port (
        dwrite  : in  std_logic_vector ( 7 downto 0);
        dread   : out std_logic_vector ( 7 downto 0);
        addr    : in  std_logic_vector ( 3 downto 0);
        nwcs    : in  std_logic;
        nrcs    : in  std_logic;
        clk     : in  std_logic;
        nreset  : in  std_logic
    );
end reg_ctrl;
   -- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

architecture struct of reg_ctrl is 
    signal write_en    : std_logic;
    signal write_clk   : std_logic;
    signal control_reg : std_logic_vector(7 downto 0);

    component reg_ctrl
    port (
        en      : in  std_logic;
        clk_in  : in  std_logic;
        clk_out : out std_logic
    );
    end component;

begin

   -- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
    i_gated1 : reg_ctrl
    port map(
        en      => write_en,
        clk_in  => clk,
        clk_out => write_clk
    );

    write_en  <= '1'         when (nwcs='0' and addr="0000") else '0';
    dread     <= control_reg when (nrcs='0' and addr="0000") else
                 "00000000";

    -- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
    process (write_clk, nreset)
    begin
        if (nreset='0') then
            control_reg <= (others => '0');
        else
            if (write_clk='1' and write_clk'event) then
                control_reg <= dwrite;
            end if;
        end if;
    end process;  
end struct;