library ieee;
use ieee.std_logic_1164.all;

entity clock  is
    port (
        clk           : in  std_logic;
        phi1          : out std_logic;
        phi2          : out std_logic
    );
end;


library ieee;
use ieee.std_logic_1164.all;

architecture simple of clock is

    signal    q0                : std_logic;
    signal    qn0               : std_logic;
    signal    q1                : std_logic;
    signal    qn1               : std_logic;
    signal    futur_q0          : std_logic;
    signal    futur_q1          : std_logic;

begin

    qn0      <= '1' when (q0='0') else '0';
    qn1      <= '1' when (q1='0') else '0';

    phi1     <= qn0 nor qn1;
    phi2     <= q0  nor q1;
    
    process(clk)
    begin
        if (clk='1' and clk'event) then
            q0 <= qn0;
        end if;
    end process;

    process(clk)
    begin
        if (clk='0' and clk'event) then
            q1 <= q0;
        end if;
    end process;

end simple;