-- //////////////////////////////////////////////////////////////////////
-- ////////////////// Dual Latchs sans reset ////////////////////////////
-- //////////////////////////////////////////////////////////////////////
library ieee;
use ieee.std_logic_1164.all;
entity dlnb21s is
    port (
        d          : in  std_logic_vector(20 downto 0);
        q          : out std_logic_vector(20 downto 0);
        enable     : in  std_logic;
        sdi        : in  std_logic;
        sdo        : out std_logic;
        testshift  : in  std_logic;
        testmode   : in  std_logic;
        phi1       : in  std_logic;
        phi2       : in  std_logic
        );
end;

library ieee, work;
use ieee.std_logic_1164.all;
use work.memories_pack.all;

architecture simple of dlnb21s is
    constant size   : integer := 21;
    
    signal  futur_d : std_logic_vector(size-1 downto 0);
    signal  mid     : std_logic_vector(size-1 downto 0);
    signal  last    : std_logic_vector(size-1 downto 0);

    signal ng_phi1    : std_logic;
    signal ng_phi2    : std_logic;
    signal en_1       : std_logic;
    signal en_2       : std_logic;
    signal lt_enable  : std_logic;
    signal x_enable   : std_logic;

begin
    futur_d   <= d when (testshift ='0')  else sdi & last(size-1 downto 1);
    x_enable  <= enable when (testshift ='0')else last(0);

    i_reg1 : ltnn21    port map(nphi=>ng_phi1, d=>futur_d, q=>mid );
    i_reg2 : ltnn21    port map(nphi=>ng_phi2, d=>mid,     q=>last);

    i_en1  : ltpn1     port map(phi =>phi1,    d=>x_enable,  q=>lt_enable);
    i_en2  : ltpn1     port map(phi =>phi2,    d=>lt_enable, q=>sdo);

    i_gate1: gated_clock port map(en=>en_1,    phi=>phi1,  gphi=>ng_phi1);
    i_gate2: gated_clock port map(en=>en_2,    phi=>phi2,  gphi=>ng_phi2);

    en_1      <=  '1'     when (testmode='1')  else enable;
    en_2      <=  '1'     when (testmode='1')  else lt_enable;
    q         <=  last;
end simple;