-- //////////////////// LTNN21 //////////////////////////
entity ltnn21 is
    port (
        phi        : in  std_logic;
        d          : in  std_logic_vector(20 downto 0);
        q          : out std_logic_vector(20 downto 0)
        );
end;

architecture simple of ltnn21 is
begin
    process(phi,d)
    begin
        if (phi='0') then  -- negative level
            q <= d;
        end if;
    end process;
end simple;

-- //////////////////// LTPN1 ///////////////////////////
entity ltpn1 is
    port (
        phi        : in  std_logic;
        d          : in  std_logic;
        q          : out std_logic
        );
end;

architecture simple of ltpn1 is
begin
    process(phi,d)
    begin
        if (phi='1') then  -- positive level
            q <= d;
        end if;
    end process;
end simple;

-- //////////////////// GATED_CLOCK /////////////////////
entity gated_clock is
    port (
        en         : in  std_logic;
        phi        : in  std_logic;
        gphi       : out std_logic
        );
end;

architecture simple of gated_clock is
begin
    gphi <= en nand phi;
end simple;