library ieee;
use ieee.std_logic_1164.all;

entity time_check is
    port (
        q1  : in  std_logic;
        q2  : in  std_logic;
        clk : in  std_logic
        );
end;

library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;

architecture simple of time_check is

    signal    q1time       : time;
    signal    q2time       : time;

    file   out_file : TEXT is out "time_check.dat";


    procedure WriteTime(constant texte : in string; constant val: in time) 
is
        variable v    : real;
        variable w    : integer;
        variable s    : line;
    begin
        v := real(val/ns);
        w := integer(v);
        write(s, texte);
        write(s, w);
        writeline(out_file, s);
    end WriteTime;

begin

    process(q1)
    begin
        if (q1'event) then
            q1time <= now;
        end if;
    end process;

    process(q2)
    begin
        if (q2'event) then
            q2time <= now;
        end if;
    end process;

    --------------------------------- TQ1Q2 ---------------------------
    process(clk)
        variable temps : time;
    begin
        if (clk='1' and clk'event) then
            temps := q2time - q1time;
            WriteTime(STRING'("TQ1Q2 : Q1 to Q2 delay "),temps);
        end if;
    end process;
end simple;