library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity compteur is
    port (
        cnt    : out  std_logic_vector(3 downto 0);
        q1     : out  std_logic;
        q2     : out  std_logic;

        clk    : in  std_logic;
        nreset : in  std_logic
        );
end;


library ieee;
use ieee.std_logic_1164.all;

architecture simple of compteur is
    signal int_cnt  : std_logic_vector(3 downto 0);
    signal inc_cnt  : std_logic_vector(3 downto 0);
    signal next_cnt : std_logic_vector(3 downto 0);
    
    signal bit0     : std_logic;
    signal bit1     : std_logic;
    signal bit2     : std_logic;
    signal bit3     : std_logic;
    
    signal int_q1   : std_logic;
    signal int_q2   : std_logic;

begin

    ----------------------------------------------------- 
    inc_cnt  <= int_cnt + "1";
    bit0     <= inc_cnt(0) after 33 ns;
    bit1     <= inc_cnt(1) after 12 ns;
    bit2     <= inc_cnt(2) after 41 ns;
    bit3     <= inc_cnt(3) after 15 ns;
    
    next_cnt <= bit3 & bit2 & bit1 & bit0;

    int_q1       <= '1' when (next_cnt="0000" or
                          next_cnt="0010" or
                          next_cnt="0100" or
                          next_cnt="0110" or
                          next_cnt="1010" or
                          next_cnt="1100" or
                          next_cnt="1110") else '0';
                          
    int_q2       <= '1' when (next_cnt="0001" or
                          next_cnt="0011" or
                          next_cnt="0101" or
                          next_cnt="0110" or
                          next_cnt="1010" or
                          next_cnt="1111" or
                          next_cnt="1101" or
                          next_cnt="0111") else '0';
                          
    q1  <= transport int_q1 after 9  ns;
    q2  <= transport int_q2 after 45 ns;
    cnt <= int_cnt;
    
    ----------------------------------------------------- 
    process(clk, nreset)
    begin
        if (nreset='0') then
            int_cnt <= (others => '0');
        else
            if (clk='1' and clk'event) then
                int_cnt <= next_cnt;
            end if;
        end if;
    end process;
    
end simple;