library ieee;
use ieee.std_logic_1164.all;

entity bench is
end;


library ieee;
use ieee.std_logic_1164.all;

architecture simple of bench is

    component compteur 
    port (
        cnt    : out  std_logic_vector(3 downto 0);
        q1     : out  std_logic;
        q2     : out  std_logic;

        clk    : in  std_logic;
        nreset : in  std_logic
        );
    end component;

    component time_check 
    port (
        q1  : in  std_logic;
        q2  : in  std_logic;
        clk : in  std_logic
        );
    end component;

    signal cnt      : std_logic_vector(3 downto 0);
    signal clk      : std_logic;
    signal nreset   : std_logic;
    signal q1       : std_logic;
    signal q2       : std_logic;

begin

    i_cnt : compteur 
    port map (
        cnt    => cnt,
        q1     => q1,
        q2     => q2,
        clk    => clk,
        nreset => nreset
        );

    i_time : time_check 
    port map (
        q1     => q1,
        q2     => q2,
        clk    => clk
        );
    
    
    process
    begin
        nreset <= '0';
        wait for 11 ns;
        nreset <= '1';
        wait;
    end process;
    
    
    process
    begin
        clk <= '0';
        wait for 500 ns;
        clk <= '1';
        wait for 500 ns;
    end process;
    
end simple;