library ieee;

use ieee.std_logic_1164.all;

entity pattgenc is
    port (
            patt_clk  : in  std_logic;
            cnt_reset : in  std_logic;
            exit_c    : in  std_logic;
            data      : out std_logic_vector( 7 downto 0)
        );
end pattgenc;


architecture c_gen  of pattgenc is
    attribute foreign          : string;
    attribute foreign of c_gen : architecture is "VHDL_IF_init 
pattgenc.so";
begin

end c_gen;