-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library ieee;
use ieee.std_logic_1164.all;

entity count4 is
    port (
        dwrite  : in  std_logic_vector ( 7 downto 0);
        dread   : out std_logic_vector ( 7 downto 0);
        addr    : in  std_logic_vector ( 3 downto 0);
        nwcs    : in  std_logic;
        nrcs    : in  std_logic;
        clk     : in  std_logic;
        nreset  : in  std_logic
    );
end count4;
   -- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

architecture struct of count4 is 
    signal int_en   : std_logic;
    signal next_en  : std_logic;
    signal int_cnt  : std_logic_vector(7 downto 0);
    signal next_cnt : std_logic_vector(7 downto 0);
    signal clear    : std_logic;
begin

   -- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
    clear     <= '1' when (int_en='0' or int_cnt="10111100") else '0';
    next_cnt  <= "00000000"        when (clear='1') else
                  int_cnt + "1";

   -- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

    next_en   <= dwrite(0) when (nwcs='0' and addr="0000") else int_en;
    dread     <= "0000000" & int_en when (nrcs='0' and addr="0000") else
                 int_cnt            when (nrcs='0' and addr="0001") else
                 "00000000";

   -- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
    process (clk, nreset)
    begin
        if (nreset='0') then
            int_cnt <= (others => '0');
            int_en  <= '0';
        else
            if (clk='1' and clk'event) then
                int_cnt <= next_cnt;
                int_en  <= next_en;
            end if;
        end if;
    end process;  
end struct;