library ieee;                                                                      
use ieee.std_logic_1164.all;                                                       
                                                                                   
entity bench_count4 is                                                             
end bench_count4;                                                                  
                                                                                   
                                                                                   
library ieee;                                                                      
use ieee.std_logic_1164.all;                                                       
use std.textio.all;                                                                
                                                                                   
architecture bench of bench_count4 is                                              
                                                                                   
    component count4                                                               
    port (                                                                         
        dwrite  : in  std_logic_vector ( 7 downto 0);                              
        dread   : out std_logic_vector ( 7 downto 0);                              
        addr    : in  std_logic_vector ( 3 downto 0);                              
        nwcs    : in  std_logic;                                                   
        nrcs    : in  std_logic;                                                   
        clk     : in  std_logic;                                                   
        nreset  : in  std_logic                                                    
    );                                                                             
    end component;                                                                 
                                                                                   
    signal dwrite   : std_logic_vector ( 7 downto 0);                              
    signal dread    : std_logic_vector ( 7 downto 0);                              
    signal addr     : std_logic_vector ( 3 downto 0);                              
    signal nwcs     : std_logic;                                                   
    signal nrcs     : std_logic;                                                   
    signal clk      : std_logic;                                                   
    signal nreset   : std_logic;                                                   
                                                                                   
    file   out_file : TEXT is out "counter.flx";                                   
                                                                                   
begin                                                                              
    -- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++          
                                                                                   
    I_cnt : count4                                                                 
    port map (                                                                     
        dwrite => dwrite,                                                          
        dread  => dread ,                                                          
        addr   => addr  ,                                                          
        nwcs   => nwcs  ,                                                          
        nrcs   => nrcs  ,                                                          
        clk    => clk   ,                                                          
        nreset => nreset                                                           
    );                                                                             
                                                                                   
    -- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++          
    process                                                                        
                                                                                   
        variable ligne : line;                                                     
                                                                                   
        procedure fprintf(constant texte : in string) is                           
        begin                                                                      
            write(ligne, texte);                                                   
            writeline(out_file, ligne);                                            
        end fprintf;                                                               
                                                                                   
                                                                                   
    -- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++          
        procedure init_file is                                                     
        begin                                                                      
            fprintf("PI dwrite<7>");                                               
            fprintf("PI dwrite<6>");                                               
            fprintf("PI dwrite<5>");                                               
            fprintf("PI dwrite<4>");                                               
            fprintf("PI dwrite<3>");                                               
            fprintf("PI dwrite<2>");                                               
            fprintf("PI dwrite<1>");                                               
            fprintf("PI dwrite<0>");                                               
            fprintf("PI addr<3>");                                                 
            fprintf("PI addr<2>");                                                 
            fprintf("PI addr<1>");                                                 
            fprintf("PI addr<0>");                                                 
            fprintf("PI nwcs<0>");                                                 
            fprintf("PI nrcs<0>");                                                 
            fprintf("PI nreset<0>");                                               
            fprintf("PO dread<7>");                                                
            fprintf("PO dread<6>");                                                
            fprintf("PO dread<5>");                                                
            fprintf("PO dread<4>");                                                
            fprintf("PO dread<3>");                                                
            fprintf("PO dread<2>");                                                
            fprintf("PO dread<1>");                                                
            fprintf("PO dread<0>");                                                
                                                                                   
        end init_file;                                                             
                                                                                   
                                                                                   
    -- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++          
        procedure printBit(constant v     : in std_logic)                          
        is                                                                         
                                                                                   
        begin                                                                      
            if (v='0') then                                                        
                write(ligne, STRING'("0 "));                                       
                                                                                   
            else                                                                   
                if (v='1') then                                                    
                    write(ligne, STRING'("1 "));                                   
                else                                                               
                    write(ligne, STRING'("X "));                                   
                end if;                                                            
                                                                                   
            end if;                                                                
        end printBit;                                                              
                                                                                   
    -- ++++++++++++++++++++++++++++++++++++++++++++++++++++++          
        procedure printVect(constant v : in std_logic_vector)                      
        is                                                                         
        begin                                                                      
            for i in v'range loop                                                  
                printBit(v(i));                                                    
            end loop;                                                              
        end printVect;                                                             
                                                                                   
                                                                                   
    -- +++++++++++++++++++++++++++++++++++++++++++++++++++++++          
        procedure ResetSys  is                                                     
        begin                                                                      
            clk    <= '0';                                                         
            wait for 100 ns;                                                       
            nrcs   <= '1';                                                         
            nwcs   <= '1';                                                         
            wait for 100 ns;                                                       
            nreset <= '0';                                                         
            wait for 100 ns;                                                       
            addr   <= "1100";                                                      
            wait for 100 ns;                                                       
            dwrite <= "11111111";                                                  
            wait for 100 ns;                                                       
            clk    <= '1';                                                         
            wait for 500 ns;                                                       
                                                                                   
            printVect(dwrite);                                                     
            printVect(addr);                                                       
            printBit (nwcs);                                                       
            printBit (nrcs);                                                       
            printBit (nreset);                                                     
            printVect("XXXXXXXX");                                                 
            writeline(out_file, ligne);                                            
                                                                                   
        end ResetSys;                                                              
                                                                                   
    -- +++++++++++++++++++++++++++++++++++++++++++++++++++++++          
        procedure writeReg(constant address : in std_logic_vector( 3 downto 0);    
                           constant data    : in std_logic_vector( 7 downto 0) )   
        is                                                                         
        begin                                                                      
            clk    <= '0';                                                         
            wait for 100 ns;                                                       
            nrcs   <= '1';                                                         
            nwcs   <= '0';                                                         
            wait for 100 ns;                                                       
            nreset <= '1';                                                         
            wait for 100 ns;                                                       
            addr   <= address;                                                     
            wait for 100 ns;                                                       
            dwrite <= data;                                                        
            wait for 100 ns;                                                       
            clk    <= '1';                                                         
            wait for 500 ns;                                                       
                                                                                   
            printVect(dwrite);                                                     
            printVect(addr);                                                       
            printBit (nwcs);                                                       
            printBit (nrcs);                                                       
            printBit (nreset);                                                     
            printVect("XXXXXXXX");                                                 
            writeline(out_file, ligne);                                            
        end writeReg;                                                              
                                                                                   
    -- +++++++++++++++++++++++++++++++++++++++++++++++++++++++          
        procedure readReg( constant address : in std_logic_vector( 3 downto 0);    
                           constant exp_data: in std_logic_vector( 7 downto 0))    
        is                                                                         
        begin                                                                      
            clk    <= '0';                                                         
            wait for 100 ns;                                                       
            nrcs   <= '0';                                                         
            nwcs   <= '1';                                                         
            wait for 100 ns;                                                       
            nreset <= '1';                                                         
            wait for 100 ns;                                                       
            addr   <= address;                                                     
            wait for 100 ns;                                                       
            dwrite <= "11111111";                                                  
            wait for 100 ns;                                                       
            clk    <= '1';                                                         
            wait for 200 ns;                                                       
            ASSERT dread = exp_data  REPORT "data reading error "                  
                SEVERITY error;                                                    
            wait for 300 ns;                                                       
                                                                                   
            printVect(dwrite);                                                     
            printVect(addr);                                                       
            printBit (nwcs);                                                       
            printBit (nrcs);                                                       
            printBit (nreset);                                                     
            printVect(exp_data);                                                   
            writeline(out_file, ligne);                                            
        end readReg;                                                               
    -- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++          
        procedure cycle  (constant n : integer)                                    
        is                                                                         
        begin                                                                      
            for i in 1 to n loop                                                   
                clk    <= '0';                                                     
                wait for 500 ns;                                                   
                clk    <= '1';                                                     
                wait for 500 ns;                                                   
                                                                                   
                printVect(dwrite);                                                 
                printVect(addr);                                                   
                printBit (nwcs);                                                   
                printBit (nrcs);                                                   
                printBit (nreset);                                                 
                printVect("XXXXXXXX");                                             
                writeline(out_file, ligne);                                        
            end loop;                                                              
                                                                                   
        end cycle;                                                                 
                                                                                   
    -- +++++++++++++++++++++++++++++++++++++++++++++++++++++++          
                                                                                   
    begin                                                                          
        init_file;                                                                 
                                                                                   
        ResetSys;                                                                  
        writeReg ("0000",   "00000000");                                           
        readReg  ("0000",   "00000000");                                           
        writeReg ("0000",   "00000001");                                           
        readReg  ("0000",   "00000001");                                           
        readReg  ("0001",   "00000010");                                           
        readReg  ("0001",   "00000011");                                           
        readReg  ("0001",   "00000100");                                           
        cycle(4);                                                                  
        readReg  ("0001",   "00001001");                                           
        readReg  ("0001",   "00001010");                                           
        readReg  ("0001",   "00001011");                                           
                                                                                   
        wait ;                                                                     
    end process;                                                                   
end bench;