-- //////////////////////////////////////////////////////////////////////
-- /////////////////////////// boundary-scan structures /////////////////
-- //////////////////////////////////////////////////////////////////////
library ieee;
use ieee.std_logic_1164.all;
entity boundary_bus40 is
port (
        din          : in  std_logic_vector(39 downto 0);
        sdi          : in  std_logic;
        testshift    : in  std_logic;
        phi1         : in  std_logic;
        phi2         : in  std_logic;
        phi_dump     : in  std_logic;
        testmode     : in  std_logic;
        sdo          : out std_logic;
        dout         : out std_logic_vector(39 downto 0)
        );
end;

library ieee, work;
use ieee.std_logic_1164.all;
use work.memories_pack.all;

architecture simple of boundary_bus40 is

    constant size   : integer := 40;
    signal   d      : std_logic_vector(size-1 downto 0);
    signal   mid    : std_logic_vector(size-1 downto 0);
    signal   q      : std_logic_vector(size-1 downto 0);
    signal   upq    : std_logic_vector(size-1 downto 0);
begin
    d    <= din   when (testshift ='0') else sdi & q(size-1 downto 1);
    sdo  <= q(0);
    dout <= upq   when (testmode='1') else din;

    -- ................... latches ...............
    i_mid : latchnb
    generic map(size=>size)
    port map(phi=>phi1, d=>d, q=>mid); 
    
    i_q : latchnb
    generic map(size=>size)
    port map(phi=>phi2, d=>mid, q=>q); 
    
    i_upq : latchnb
    generic map(size=>size)
    port map(phi=>phi_dump, d=>q, q=>upq); 

end simple;