library ieee;
use ieee.std_logic_1164.all;

entity filtre is
    port (
        d      : in  std_logic;
        q      : out std_logic;
        clk    : in  std_logic;
        nreset : in  std_logic
        );
end;

library ieee;
use ieee.std_logic_1164.all;

architecture simple of filtre is

    signal f0              : std_logic;
    signal f1              : std_logic;
    signal f2              : std_logic;
    signal next_f2         : std_logic;
begin
    next_f2        <= f1 when (f1=f0) else f2;
    
    process(clk, nreset)
    begin
        if (nreset='0') then
            f0 <= '0';
            f1 <= '0';
            f2 <= '0';
        else
            if (clk='1' and clk'event) then
                f0 <= d;
                f1 <= f0;
                f2 <= next_f2;
            end if;
        end if;
    end process;
    
    q <= f2;
end simple;